1. Field of the Invention
The present invention generally relates to semiconductor packages and fabrication methods thereof, and more particularly to a non-carrier type semiconductor package and a fabrication method thereof.
2. Description of the Prior Art
Conventionally, a semiconductor package is often formed by using a lead frame as a chip carrier. The leadframe comprises a die pad and a plurality of leads formed around the periphery of the die pad. The lead-frame based semiconductor package is formed by attaching a semiconductor chip to the die pad and electrically connecting the semiconductor chip to the leads via the bonding wires, followed by forming an encapsulant to encapsulate the chip, die pad, bonding wires and the inner portions of the leads.
There are a great variety of lead frame based semiconductor packages, such as quad flat non-leaded (QFN) semiconductor package. The main characteristic feature of this QFN semiconductor package is that, unlike a quad flat package (QFP), it does not have external gull wing shaped leads being formed outside the package for electrically connecting with external devices, therefore, the finished QFN package is substantially smaller. As shown in FIG. 1, the bottom surfaces of both the lead frame die pad 11 and the leads 12 of the QFN semiconductor package 1 are exposed from an encapsulant 15. This allows the semiconductor chip 13, which is mounted on the die pad 11 and electrically connected to the leads 12 via the bonding wires 14, to be electrically connected to an external device, such as printed circuit board 20, through electrically connecting the exposed surface of the leads to the solder pads 100 on the external device via a solder material 16.
In addition, with the increasing demands for light-weighted and low-profiled semiconductor packages, the conventional lead frame based semiconductor package can not meet the demand for a further reduction in package size, therefore the industry has developed a non-carrier type semiconductor package that the overall thickness of the package can be reduced significantly by eliminating the use of a lead frame.
Referring to FIG. 2, a non-carrier type semiconductor package disclosed by U.S. Pat. No. 5,830,800 is illustrated herein. This semiconductor package is formed by first forming a plurality of electroplating solder pads 21 on a copper carrier (not shown in the FIG.) according to the circuit layout design. The plating layer for forming the solder pads 21 is a metal layer consisting of gold/palladium/nickel/palladium (Au/Pd/Ni/Pd) with a thickness of about 6 μm. Then, a chip 22 is mounted on the carrier followed by a wire bonding process to establish electrical connections by using bonding wires 23. After that, an encapsulant 24 is formed by a molding process, and then the copper carrier is removed to expose the electroplating solder pads 21. In such ways, the semiconductor package without a chip carrier is formed, which can be electrically connected to an external device such as a printed circuit board 20 via the solder joints 26, formed to bond the exposed solder pads 21 and the bond pads 200 of the external device via a solder material.
However, when a highly integrated chip, namely, the chip has a high density layout of electronic elements is used in the aforementioned QFN semiconductor package and the non-carrier type semiconductor package, comparatively large numbers of leads or electroplating solder pads for the corresponding electrical connections are required, and as a result, the package size need to increase to accommodate more I/O and then the loop length of the bonding wires and the distance between the chip and the leads or the electroplating solder pads are increased, and consequently, not only increase the difficulties of bonding wire operation, but also easily cause problems such as bonding wire shift and short circuit, thus seriously degrading the quality of electrical connections.
In views of the aforementioned drawbacks, the claim of the U.S. Pat. No. 6,884,652 discloses a semiconductor package that is capable of effectively shortening the bonding wire loop length. As shown in the FIG. 3, the semiconductor package comprises: a dielectric layer 30, wherein, a plurality of through holes 300 are formed at predetermined positions therein; a solder 31, which is applied in each through holes 300 of the dielectric material layer; a first thin copper layer 32, formed on the dielectric material layer 30 and the solder 31; a second copper layer 33, applied on the top of the first thin copper layer 32 allowing a plurality of conductive traces 330 to be formed on the first copper layers 32, and each of the conductive traces 330 has a terminal 331; a metallic layer 34, which is applied on each terminal 331 of the conductive traces 330; at least a chip 35, attached on a predetermined location of the conductive traces 330 by an adhesive; a plurality of bonding wires 36, for electrically connecting the chip 35 to the terminal 331 that has a metallic layer 34 atop; and an encapsulant 37, for encapsulating the chip 35, bonding wires 36 and conductive traces 330, allowing the dielectric material layer 30 and the solder 31 to be exposed from the encapsulant 37.
The advantage of the aforementioned semiconductor package is that it does not require a lead frame or a substrate to function as the chip carrier, and the conductive traces can be flexibly distributed in correspondence to the design of chip and then the terminal 331 with the metallic layer 34 can be much closer to the wire bonding disposing region on the chip, therefore, the loop length of the bonding wire for electrically connecting the chip to the terminal of the conductive trace, consequently can be shortened, thereby, enhancing circuit layout flexibility, electrical connection quality and performance of the semiconductor package.
However, regardless of the aforementioned QFN or non-carrier type semiconductor packages, when the semiconductor package is electrically connected to the printed circuit board by means of the surface mounting technology (SMT) via the reflowed solder forming the solder joints, due to the different materials of the semiconductor package and the printed circuit board, there is a thermal stress formed between the semiconductor package and the printed circuit board. The thermal stress is in direct proportion to the difference between the thermal expansion coefficients of the semiconductor package and the printed circuit board, and in inverse proportion to the height of the solder joint. The thermal stress of solder joint is in direct formulated as ((α2−α1)ΔTδ1)/h, wherein the (α2−α1) is the coefficient of thermal expansion difference between the semiconductor package and the printed circuit board, the ΔT is the maximum temperature difference between the semiconductor package and the printed circuit board, the δ1 is the distance between the center of the semiconductor package and the location of solder joint, and the h is the height of solder joint. Consequently, in the aforementioned semiconductor package of the prior art, since the solder joint height is very low, the solder joint would suffer a great amount of thermal stress. In this situation, it would not only reduce the fatigue life of the solder joint, but further cause the problem of crack of the solder joint, therefore seriously affecting the reliability of the electronic products. Comparatively, when the height and amount of the solder are increased, the excessive amount of solder or improper control over mounting between the semiconductor package and the printed circuit board would cause neighboring solder to contact each other which would further cause short circuit and bring defects in fabrication.
Hence, it is a highly urgent issue in the industry to provide a non-carrier type semiconductor package and a fabrication method thereof, which can effectively solve the aforementioned drawbacks of the prior arts, such as solder joint crack and poor reliability of the electronic products, as well as increase circuit layout flexibility and shorten the bonding wires loop length.